Cole
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http://theinquirer.net/?article=26317
"CHIP FIRM Intel said it is developing an ultra low power version of the 65 nanometre process technology specifically for notebooks and other small devices.
The firm said that with transistors on some chips over the billion mark, it has developed tech which it claims will cut down leakage by 1000 times.
But it's not being very forthcoming about the details - merely saying that the ultra low power process has trannie modifications intended to reduce sub threshold leakage, junction leakage, and gate oxide leakage.
The 65 nanometre chips have 35 nanometre gate lengths, which Intel said will be the smallest and highest performing CMOS devices to be made in high volume.
The chips will include a second gen version of strained silicon, which gives higher drive current and increases transistor speed, while only raising the manufacturing cost by two per cent. µ"
"CHIP FIRM Intel said it is developing an ultra low power version of the 65 nanometre process technology specifically for notebooks and other small devices.
The firm said that with transistors on some chips over the billion mark, it has developed tech which it claims will cut down leakage by 1000 times.
But it's not being very forthcoming about the details - merely saying that the ultra low power process has trannie modifications intended to reduce sub threshold leakage, junction leakage, and gate oxide leakage.
The 65 nanometre chips have 35 nanometre gate lengths, which Intel said will be the smallest and highest performing CMOS devices to be made in high volume.
The chips will include a second gen version of strained silicon, which gives higher drive current and increases transistor speed, while only raising the manufacturing cost by two per cent. µ"
